Trying to preserve other peoples code

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Summary

CRC Generator for Verilog or VHDL CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible. To build on linux using gcc: g++ -o crc_gen crc_gen.cpp Invoke the tool via command line: ./crc_gen [language] [data_width] [poly_width] [poly_string] Options: language: verilog or vhdl data_width: data bus width ${1..1024}$ poly_width: polynomial width ${1..1024}$ poly_string: a string that describes CRC polynomial, eg: Ethernet MAC FCS uses poly 04C11DB7 Examples: $05 = x^5+x^2+1$ $8005 = x^{16} + x^{15}+ x^2+ 1$ The string representation (0x05, 0x8005) doesn’t include highest degree coefficient in polynomial representation ($x^5$ and $x^{16}$ in the above examples). Printing usage: ./crc_gen usage: crc-gen language data_width poly_width poly_string parameters: language : verilog or vhdl data_width : data bus width {1..1024} poly_width : polynomial width {1..1024} poly_string : polynomial string in hex example: usb crc5 = x^5+x^2+1 crc-gen verilog 8 5 05 Generation in action: ./crc_gen verilog 2 4 3 //----------------------------------------------------------------------------- // Copyright (C) 2009 OutputLogic.com // This source file may be used and distributed without restriction // provided that this copyright statement is not removed from the file // and that any derivative work contains the original copyright notice // and the associated disclaimer. // THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS // OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED // WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. //----------------------------------------------------------------------------- // CRC module for // data[1:0] // crc[3:0]=1+x^1+x^4; // module crc( input [1:0] data_in, input crc_en, output [3:0] crc_out, input rst, input clk); reg [3:0] lfsr_q, lfsr_c; assig...

First seen: 2026-05-26 14:35

Last seen: 2026-05-26 15:36