My DIY FPGA board can run Quake II

Summary

My DIY FPGA board can run Quake II (part 4) 22-mar-2026 Time to design a new board I didn’t want to simply recreate what I had before. Making something more advanced meant soldering BGA. I wasn’t sure if I could do it, but I decided to try anyway. Specifically, I wanted a more advanced FPGA – I chose the Efinix Ti60F256 – and more modern memory – IM8G16D3FFBG, which is a 1GB DDR3L chip. The first has 256 pins and the second has 96, both with a 0.8 mm pitch. Some IC in BGA-256 package. Not Ti60 though, but looks very similar. After the struggles with DDR1, I had absolutely no desire to reinvent the memory controller. Fortunately, I found something with the promising name “DDR3 Soft Controller Core” on the Efinix website. On their community forum, I was also pointed to a guide on DDR3 PCB layout recommendations. There were new unfamiliar terms, so I had to spend more time diving into the theory. I barely managed to meet the trace length matching requirements. The recommendations also suggested routing all address and command lines on a single layer, but that seemed impossible. Instead, I tried to account for the difference in signal propagation speeds across different layers and compensated by shortening the traces on the internal layer. This time the PCB has 6 layers I studied the recommendations for the quantity and values of the decoupling capacitors on the power inputs. However, I still couldn’t follow them strictly; that many components simply wouldn’t fit physically near the power pins, and I really didn’t want to solder anything smaller than 0603 (i.e. 0.06” x 0.03” — 1.6 x 0.8 mm). I just squeezed in as many as I could. Capacitors on the back of the board under FPGA, 3d model Other changes compared to the previous board: A separate TMDS serializer chip (TFP410) to avoid those green artifacts. A current limiter for connected USB devices. The ability to switch the SD card data line voltage from 3.3V to 1.8V. Potentially, this allows to increase the data transfer...