Aegis – open-source FPGA silicon

Summary

Aegis is a fully open-source FPGA, from the silicon up. Existing open-source FPGA efforts either reverse-engineer proprietary architectures (Project IceStorm, Apicula) or build tooling around closed silicon (Yosys, nextpnr). The silicon itself has always been proprietary. Aegis starts at the other end: the fabric design is open, the toolchain is open, and the path to real silicon goes through open PDKs and shuttle services like wafer.space. The project generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape out the fabric itself to a foundry. The first Aegis device, targeting GF180MCU via wafer.space. Resource Count LUT4 ~2880 BRAM (128x8) 128 tiles DSP18 (18x18 MAC) 64 tiles I/O pads 224 SerDes 4 Clock tiles 2 (8 outputs) Routing tracks 4 per edge nix build .#terra-1 # Generate IP (SV, JSON, chipdb, techmap) nix build .#terra-1-tapeout # Full RTL-to-GDS for fab submission Each device gets a complete FPGA toolchain via the tools output: # Synthesize a Verilog design to Aegis cells yosys -c synth.tcl # using $tools/share/yosys/aegis/*_cells.v + *_techmap.v # Place and route on the fabric nextpnr-aegis-terra_1 --json design_mapped.json --write design_pnr.json # Pack into a bitstream terra_1-pack --pnr design_pnr.json --output design.bin # Simulate with the bitstream loaded terra_1-sim --bitstream design.bin --cycles 1000 --vcd waves.vcd The tapeout pipeline synthesizes the FPGA fabric itself to PDK standard cells: nix build .#terra-1-tapeout ls result/ # terra_1_synth.v — gate-level netlist (Yosys) # terra_1_final.def — placed & routed layout (OpenROAD) # terra_1.gds — GDS2 for fab submission # terra_1_layout.png — layout render # timing.rpt — timing analysis # power.rpt — power report Supports GF180MCU (wafer.space) and Sky130 PDKs. Requires Nix with flakes enabled. # Build the default package (aegis-ip-tools) nix build # Build Terra 1 IP nix build .#terr...