Circuit-level PDP-11/34 emulator

Summary

ll/34 is a circuit-level emulator for the PDP-11/34A (1976), running a virtual CPU reverse-engineered from the schematics, microcode, and logic captures of an actual PDP-11/34A. It was originally designed as a digital replica of the real CPU to assist with troubleshooting at the signal level. The virtual KD11-EA CPU essentially consists of a C translation of the schematics, and lookups to the ROM tables. All combinational ROMs are reverse-engineered, and the clock generator is precisely modeled. Circuit-level (ROM truth tables + combinatorial logic) was chosen other gate-level (Verilog) because it is low-level enough to reproduce hardware bugs, yet fast enough to run programs. UNIBUS backplane (timing and signal accurate) KD11-EA CPU (circuit-level) M9301 boot card with original boot and diagnostic ROMs DL11 serial card (timing accurate) KW11 line clock (50/60 Hz) Programmer Console (including maintenance mode for CPU troubleshooting) RK05 drives (high-level emulation of the RK11 controller) RL01 and RL02 drives (high-level emulation of the RL11 controller) Tape reader VT100 terminal with stdio, TCP port or PTY modes All devices are plugged into the UNIBUS backplane (unibus.c), which performs address decoding, timing, and bus cycles. Internally, the CPU is composed of the following components: File Description ucode_rom.h 512x48-bit microcode store (bipolar PROMs), based on Bitsavers Verilog and dumps. Each micro-word controls the ALU, scratchpad, bus interface, and branching for one micro-cycle. combo_roms.h Combinational ROMs (E51-E83, E107), IR decode (E59/E60/E63/E69/E70/E71/E74), ALU function select (E61/E82/E83), trap/service priority (E52/E53), and condition code logic (E68/E107), all reconstituted from the schematics and logic captures. Open-collector ROMs wire-OR onto the MPC bus. kd11ea.c Datapath engine. Steps through the microcode one micro-word per cycle. Basic 74xx gates are simulated using C logic operators (!, &&, >> etc.). The 74S181 bit-slice ALU i...